Develop and execute verification plans for digital designs.
Create and implement testbenches using SystemVerilog and UVM methodology.
Perform functional verification, simulation, and formal verification to identify and resolve design issues.
Collaborate with hardware, software, and firmware teams for comprehensive verification coverage.
Location: Jerusalem or Petah Tikva.

7+ years of experience as a verification engineer. Proficient in SystemVerilog and UVM methodology – MUST. Strong debugging and problem-solving skills.